1. Field of the Invention
The present invention relates to the field of memory chips.
2. Discussion of Related Art
A known integrated memory IC 100 that is a writeable memory of the DRAM type is shown in FIG. 1. Such a dynamic random access memory (DRAM) chip 100 includes a plurality of memory storage cells 102 in which each cell 102 has a transistor 104 and an intrinsic capacitor 106. As shown in FIGS. 2 and 3, the memory storage cells 102 are arranged in arrays 108, wherein memory storage cells 102 in each array 108 are interconnected to one another via columns of conductors 110, known as bitlines, and rows of conductors 112, known as wordlines. One half of the memory storage cells 102 are connected to a bitline while the remainder of the memory storage cells are connected to a complementary bit line. As shown in FIG. 4, the transistors 104 are used to charge and discharge the capacitors 106 to certain voltage levels. The capacitors 106 then store the voltages as binary bits, 1 or 0, representative of the voltage levels. The binary 1 is referred to as a xe2x80x9chighxe2x80x9d and the binary 0 is referred to as a xe2x80x9clow.xe2x80x9d The voltage value of the information stored in the capacitor 106 of a memory storage cell 102 is called the logic state of the memory storage cell 102.
As shown in FIGS. 1 and 2, the memory chip 100 includes six address input contact pins A0, A1, A2, A3, A4, A5 along its edges that are used for both the row and column addresses of the memory storage cells 102. The row address strobe (RAS) input pin receives a signal RAS that clocks the address present on the DRAM address pins A0 to A5 into the row address latches 114. Similarly, a column address strobe (CAS) input pin receives a signal CAS that clocks the address present on the DRAM address pins A0 to A5 into the column address latches 116. The memory chip 100 has data pin Din that receives data and data pin Dout that sends data out of the memory chip 100. The modes of operation of the memory chip 100, such as Read, Write and Refresh, are well known and so there is no need to discuss them for the purpose of describing the present invention.
A variation of a DRAM chip is shown in FIGS. 5 and 6. In particular, by adding a synchronous interface between the basic core DRAM operation/circuitry of a second generation DRAM and the control coming from off-chip a synchronous dynamic random access memory (SDRAM) chip 200 is formed. The SDRAM chip 200 includes a bank of memory arrays 208 wherein each array 208 includes memory storage cells 210 interconnected to one another via columns and rows of conductors.
As shown in FIGS. 5 and 6, the memory chip 200 includes twelve address input contact pins A0-A11 that are used for both the row and column addresses of the memory storage cells of the bank of memory arrays 208. The row address strobe (RAS) input pin receives a signal RAS that clocks the address present on the DRAM address pins A0 to A11 into the bank of row address latches 214. Similarly, a column address strobe (CAS) input pin receives a signal CAS that clocks the address present on the DRAM address pins A0 to A11 into the bank of column address latches 216. The memory chip 200 has data input/output pins DQ0-15 that receive and send input signals and output signals. The input signals are relayed from the pins DQ0-15 to a data input register 218 and then to a DQM processing component 220 that includes DQM mask logic and write drivers for storing the input data in the bank of memory arrays 208. The output signals are received from a data output register 222 that received the signals from the DQM processing component 220 that includes read data latches for reading the output data out of the bank of memory arrays 208. The modes of operation of the memory chip 200, such as Read, Write and Refresh, are well known and so there is no need to discuss them for the purpose of describing the present invention.
In both of the memory chips 100 and 200 of FIGS. 1-6, the corresponding memory arrays 108, 208 are connected to sensing amplifiers 300. An example of a known sensing amplifier 300 is shown within the rectangular dashed line box of FIG. 7 and includes primary pass transistors 302, 304 and secondary pass transistors 306, 308, 310. Each of the pass transistors of the sensing amplifier 300 is controlled by bitlines 110, 312 and the MUX (xe2x80x9cmultiplexedxe2x80x9d) and EQ (xe2x80x9cequalizedxe2x80x9d) signals shown in FIG. 7. As shown in FIG. 7, the sensing amplifier 300 further includes criss-crossed transistors 314 that are connected with the bitline 110 and the complementary bitline 312 and receive the signals NSET and PSET. The sensing amplifier 300 detects small voltage differences between the bitlines 110 and the complementary bitlines 312.
In operation, the bitlines 110 and the complementary bitlines 312 are equalized to a voltage level VBLEQ prior to the activation of a wordline 112 as shown in FIG. 8. While the bitlines 110 and the complementary bitlines 312 are equalized, the gate voltages MUX and EQ of the gates of the pass transistors 302, 304, 306, 308, 310 are set at a common voltage of VINT, the voltage of the internal voltage supply, as shown in FIG. 8. Note that the MUX signal is used to determine which one of a pair of bitlines to which the signals NSET and PSET are applied.
Once a wordline 112 is activated, a number of events occur. For example, selection of a wordline 112 causes all memory cells connected to the wordline 112 to be opened. In addition, the open memory cells are connected to bitlines that are connected to sense amplifiers. A small charge or data is temporarily stored in capacitor 106 where it can be passed onto the bitline. The small charge or data stored in the memory storage cells 102, 210 is passed onto the drain D of the transistor 104 and then placed on one of the complementary bitlines 312 via the transistors 302, 304. Since the stored charge is placed on the complementary bitlines 312 and not the bitlines 110, a small voltage difference between the bitlines 312 and the bitlines 110 results. The small voltage difference is detected by the sensing amplifier 300 which restores or writesback the charge/data placed on the complementary bitlines 312 by driving one of the complimentary bitlines 312 to a high state voltage VBLH and the corresponding bitline 110 to a low state voltage, such as ground GND, as shown in FIG. 8. The sensing amplifier 300 restores the charge by having the signal PSET move from its normal voltage of VBLEQ to a high voltage while the other signal NSET moves from its normal voltage of VBLEQ to a low voltage. Having the signals NSET and PSET at high and low states causes the transistors 314 to drive a bitline all the way to either a high state or a low state and drive the complimentary bitline all the way to the opposite state. While the bitline 110 and complimentary bitline 312 are driven to different voltages, the voltage EQ is driven down to the low state voltage, such as GND, and the voltage MUX is driven up to the value VPP as shown in FIG. 8.
While the above description regards the situation where the charge or data is placed on a complementary bitline 312 and written back by applying a high state voltage to the complementary bitline 312, it is also possible that the charge or data is placed on and written back onto the bitline 110 via a process that is complementary to the one described above. In either scenario, the sensing amplifier 300 does not know whether the bitline 110 or the complementary bitline 312 is connected to the memory storage cell 102, 210. In this situation, the charge in the memory storage cell causes the bitline that is connected to the memory storage cell to be driven to the voltage level of that charge while the other bitline is driven to an equal, but opposite, voltage as shown in FIG. 8.
Due to the structure of the memory arrays 108, 208 described previously, the pass transistors 302, 304, 306, 308, 310 connect only one of the bitlines 110 and its corresponding complimentary bitline 312 to the memory storage cell 102. Another property of the memory cells 108, 208 is that the bitlines 110 and their complimentary bitlines 312 contain parasitic resistance and capacitance. Thus, when the bitlines 110 or complimentary bitlines 312 are switched from one voltage to another, the associated parasitic resistance and capacitance will cause a power loss for the particular bitline experiencing a switch in voltage. In the known process shown in FIG. 8, bitline 110 and its corresponding complimentary bitline 312, each experience a switch in voltage and, thus, each causes an undesired power loss.
One aspect of the present invention regards a memory system that includes an array of memory storage cells that has a memory storage cell. A first bitline is connected to the memory storage cell and a second bitline complementary to the first bitline not connected to the memory storage cell. A sensing amplifier is connected to the first bitline and the second bitline so as to detect a charge present on the first bitline, wherein the sensing amplifier receives signals that indicate that the first bitline is connected to the memory storage cell, wherein the sensing amplifier prevents a portion of the second bitline from being driven to a full voltage state based on receipt of the signals.
A second aspect of the present invention regards a method of transferring data to a memory storage cell that is attached to a first bitline. The method includes passing a charge representative of data from a memory storage cell to a first bitline that is connected to the memory storage cell and detecting that the charge is on the first bitline. Upon detecting the charge is on the first bitline, preventing a portion of a second biltline that is complementary to the first bitline from being driven to a full voltage state.
Each of the above aspects of the present invention provides the advantage of increasing power savings by reducing parasitic losses during recharging of a memory storage cell.